Mario Porrmann

Dynamically Reconfigurable Hardware for Satellite Payload Processing

Reconfigurable hardware is gaining a steadily growing interest in the domain of space applications. The ability to reconfigure the information processing infrastructure at runtime together with the high computational power of today’s FPGA architectures at relatively low power makes these devices interesting candidates for data processing in space applications. Partial dynamic reconfiguration of FPGAs enables maximum flexibility and can be utilized for performance increase, for improving energy efficiency, and for enhanced fault tolerance. To be able to prove the effectiveness of these novel approaches for satellite payload processing, a highly scalable prototyping environment has been developed, combining dynamically reconfigurable FPGAs with the required interfaces such as SpaceWire, MIL-STD-1553B, and SpaceFibre. For enhanced fault tolerance, blind and readback scrubbing is supported and the scrub rate can be adapted individually for different parts of the design. While the focus is on prototyping and analysis of the new features that are enabled by dynamic reconfiguration, like extended lifetime, enhanced reliability, and fault tolerance at low power, a clear migration path towards future flight versions is foreseen.

About Mario Porrmann:
Mario Porrmann is “Akademischer Direktor” in the research group Cognitronics and Sensor Systems, Center of Excellence Cognitive Interaction Technology, Bielefeld University, Germany. He graduated as “Diplom‐Ingenieur” in Electrical Engineering at the University of Dortmund, Germany, in 1994. In 2001 he received a PhD in Electrical Engineering from the University of Paderborn, Germany for his work on performance evaluation of embedded neurocomputers. From 2001 to 2009 he was senior lecturer and from 2010 to March 2012 Acting Professor of the research group System and Circuit Technology at the Heinz Nixdorf Institute, University of Paderborn. Mario Porrmann`s main scientific interests are in on‐chip multiprocessor systems, dynamically reconfigurable computing, and resource‐efficient as well as fault‐tolerant computer architectures.