Invasive Computing – The Quest for Many-Core Efficiency and Predictability
Technology roadmaps foresee 1000 and more processors being integrated in a single MPSoC in the year 2020. For such systems, the control of multiple concurrent applications can obviously not be organized in a fully centralized way any more as it is done today. In this talk, we present present <invasive computing> as a new paradigm for an application-driven, decentralized as well as resource-aware organization of concurrent applications on future large scale MPSoCs. The main goal of invasive computing is to provide scalable efficiency and at the same time more predictability of parallel computing on multi-core systems including execution time, power and safety aspects.
Conceptually, efficiency may be raised if temporal computational needs of an application may be translated into a dynamic reservation of exclusive resources. The result of an invasion phase is a so-called claim of resources. After termination of a computationally demanding execution phase, the application may release the resources again back to the pool in a phase called retreat.
Through the exclusiveness of provided resources including not only processors, but also memory access and communication bandwidth on a network on chip, a much higher predictability of non-functional properties shall become possible as well. In the talk, we provide results of the DFG-funded collaborative reseach center TR89 on invasive computing including a) a language definition and implementation for invasive computing based on X10 as developed by IBM. Moreover, we will show how invasive programs may be b) efficiently simulated so to have a testbed for invasive application developers, resource-aware programming, and design space exploration of architectural tradeoffs such as numbers and types of processors, and memory organization. Finally, c) a real-time video application is used to show that predictable throughput processing may be achieved on invasive massively parallel target architectures called tightly-coupled processor arrays (TCPAs) even for varying number of available processors at run-time by exploiting and proposing a claim-dependent selection of video processing algorithm to be executed as a QoS tradeoff with image quality.
About Jürgen Teich:
Jürgen Teich (Senior Member, IEEE) received the M.S. degree (Dipl.-Ing.; with honors) from the University of Kaiserslautern, Germany, in 1989 and the Ph.D. degree (summa cum laude) from the University of Saarland, Saarbruecken, Germany, in 1993. In 1994, he joined the DSP design group of Prof. E. A. Lee in the Department of Electrical Engineering and Computer Sciences (EECS), University of California at Berkeley (PostDoc). From 1995 to 1998, he held a position at the Institute of Computer Engineering and Communications Networks Laboratory (TIK), ETH Zurich, Switzerland (Habilitation). From 1998 to 2002, he was Full Professor in the Electrical Engineering and Information Technology Department, University of Paderborn, Germany. Since 2003, he has been Full Professor in the Department of Computer Science, University of Erlangen-Nuremberg, Erlangen, Germany, holding a chair in Hardware/Software Co-Design. In 2011, he was elected member of the Academia Europaea. Since 2010, he has also been the coordinator of the Transregional Research Center 89 on Invasive Computing funded by the German Research Foundation (DFG).